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s9kea128p80m48sf0 kea128 sub-family data sheet supports the following: s9keaz64amlk(r), s9keaz128amlk(r), s9keaz64avlk(r), s9keaz128avlk(r), s9keaz64aclk(r), s9keaz128aclk(r), s9keaz64amlh(r), s9keaz128amlh(r), s9keaz64avlh(r), s9keaz128avlh(r), S9KEAZ64ACLH(r) and s9keaz128aclh(r) key features ? operating characteristics C voltage range: 2.7 to 5.5 v C flash write voltage range: 2.7 to 5.5 v C temperature range (ambient): -40 to 125c ? performance C up to 48 mhz arm? cortex-m0+ core C single cycle 32-bit x 32-bit multiplier C single cycle i/o access port ? memories and memory interfaces C up to 128 kb flash C up to 16 kb ram ? clocks C oscillator (osc) - supports 32.768 khz crystal or 4 mhz to 24 mhz crystal or ceramic resonator; choice of low power or high gain oscillators C internal clock source (ics) - internal fll with internal or external reference, 37.5 khz pre-trimmed internal reference for 48 mhz system clock C internal 1 khz low-power oscillator (lpo) ? system peripherals C power management module (pmc) with three power modes: run, wait, stop C low-voltage detection (lvd) with reset or interrupt, selectable trip points C watchdog with independent clock source (wdog) C programmable cyclic redundancy check module (crc) C serial wire debug interface (swd) C aliased sram bitband region (bit-band) C bit manipulation engine (bme) ? security and integrity modules C 80-bit unique identification (id) number per chip ? human-machine interface C up to 71 general-purpose input/output (gpio) C two 32-bit keyboard interrupt modules (kbi) C external interrupt (irq) ? analog modules C one up to 16-channel 12-bit sar adc, operation in stop mode, optional hardware trigger (adc) C two analog comparators containing a 6-bit dac and programmable reference input (acmp) freescale semiconductor document number s9kea128p80m48sf0 data sheet: technical data rev 4, 09/2014 freescale reserves the right to change the detail specifications as may be required to permit improvements in the design of its products. ? 2014 freescale semiconductor, inc.
? timers C one 6-channel flextimer/pwm (ftm) C two 2-channel flextimer/pwm (ftm) C one 2-channel periodic interrupt timer (pit) C one pulse width timer (pwt) C one real-time clock (rtc) ? communication interfaces C two spi modules (spi) C up to three uart modules (uart) C two i2c modules (i2c) C one mscan module (mscan) ? package options C 80-pin lqfp C 64-pin lqfp kea128 sub-family data sheet, rev4, 09/2014. 2 freescale semiconductor, inc.
table of contents 1 ordering parts....................................................................................... 4 1.1 determining valid orderable parts............................................... 4 2 part identification................................................................................. 4 2.1 description................................................................................... 4 2.2 format.......................................................................................... 4 2.3 fields............................................................................................ 4 2.4 example....................................................................................... 5 3 ratings.................................................................................................. 5 3.1 thermal handling ratings............................................................. 5 3.2 moisture handling ratings............................................................ 5 3.3 esd handling ratings................................................................... 6 3.4 voltage and current operating ratings.......................................... 6 4 general................................................................................................. 7 4.1 nonswitching electrical specifications........................................ 7 4.1.1 dc characteristics.......................................................... 7 4.1.2 supply current characteristics........................................ 13 4.1.3 emc performance.......................................................... 15 4.2 switching specifications.............................................................. 15 4.2.1 control timing................................................................ 15 4.2.2 ftm module timing....................................................... 16 4.3 thermal specifications................................................................. 17 4.3.1 thermal characteristics.................................................. 17 5 peripheral operating requirements and behaviors................................ 19 5.1 core modules............................................................................... 19 5.1.1 swd electricals ............................................................. 19 5.2 external oscillator (osc) and ics characteristics....................... 20 5.3 nvm specifications..................................................................... 22 5.4 analog.......................................................................................... 23 5.4.1 adc characteristics....................................................... 23 5.4.2 analog comparator (acmp) electricals......................... 25 5.5 communication interfaces........................................................... 26 5.5.1 spi switching specifications.......................................... 26 5.5.2 mscan......................................................................... 29 6 dimensions........................................................................................... 29 6.1 obtaining package dimensions.................................................... 29 7 pinout................................................................................................... 30 7.1 signal multiplexing and pin assignments.................................... 30 8 revision history................................................................................... 30 kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 3
ordering parts 1.1 determining valid orderable parts valid orderable part numbers are provided on the web. to determine the orderable part numbers for this device, go to freescale.com and perform a part number search for the following device numbers: keaz128. part identification 2.1 description part numbers for the chip have fields that identify the specific part. you can use the values of these fields to determine the specific part you have received. 2.2 format part numbers for this device have the following format: q b kea a c fff m t pp n 2.3 fields this table lists the possible values for each field in the part number (not all combinations are valid): field description values q qualification status ? s = automotive qualified ? p = prequalification b memory type ? 9 = flash kea kinetis auto family ? kea a key attribute ? z = m0+ core ? f = m4 w/ dsp & fpu ? c= m4 w/ ap + fpu c can availability ? n = can not available ? (blank) = can available table continues on the next page... 1 2 ordering parts kea128 sub-family data sheet, rev4, 09/2014. 4 freescale semiconductor, inc.
field description values fff program flash memory size ? 128 = 128 kb m maskset revision ? a = 1 st fab version ? b = revision after 1 st version t temperature range (c) ? c = C40 to 85 ? v= C40 to 105 ? m = C40 to 125 pp package identifier ? lh = 64 lqfp (10 mm x 10 mm) ? lk = 80 lqfp (14 mm x 14 mm) n packaging type ? r = tape and reel ? (blank) = trays 2.4 example this is an example part number: s9keaz128amlk ratings 3.1 thermal handling ratings symbol description min. max. unit notes t stg storage temperature C55 150 c 1 t sdr solder temperature, lead-free 260 c 2 1. determined according to jedec standard jesd22-a103, high temperature storage life . 2. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 3.2 moisture handling ratings symbol description min. max. unit notes msl moisture sensitivity level 3 1 1. determined according to ipc/jedec standard j-std-020, moisture/reflow sensitivity classification for nonhermetic solid state surface mount devices . 3 ratings kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 5
3.3 esd handling ratings symbol description min. max. unit notes v hbm electrostatic discharge voltage, human body model C6000 +6000 v 1 v cdm electrostatic discharge voltage, charged-device model C500 +500 v 2 i lat latch-up current at ambient temperature of c C100 +100 ma 3 1. determined according to jedec standard jesd22-a114, electrostatic discharge (esd) sensitivity testing human body model (hbm) . 2. determined according to jedec standard jesd22-c101, field-induced charged-device model test method for electrostatic-discharge-withstand thresholds of microelectronic components . 3. determined according to jedec standard jesd78d, ic latch-up test . the test produced the following results: ? test was performed at 125 c case temperature (class ii). ? i/o pins pass +100/-100 ma i-test with i dd current limit at 400 ma (v dd collapsed during positive injection). ? i/o pins pass +50/-100 ma i-test with i dd current limit at 1000 ma for v dd . ? supply groups pass 1.5 v ccmax . ? reset_b pin was only tested with negative i-test due to product conditioning requirement. 3.4 voltage and current operating ratings absolute maximum ratings are stress ratings only, and functional operation at the maxima is not guaranteed. stress beyond the limits specified in the following table may affect device reliability or cause permanent damage to the device. for functional operating conditions, refer to the remaining tables in this document. this device contains circuitry protecting against damage due to high static voltage or electrical fields; however, it is advised that normal precautions be taken to avoid application of any voltages higher than maximum-rated voltages to this high-impedance circuit. reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level (for instance, either v ss or v dd ) or the programmable pullup resistor associated with the pin is enabled. table 1. voltage and current operating ratings symbol description min. max. unit v dd digital supply voltage C0.3 6.0 v i dd maximum current into v dd 120 ma v in input voltage except true open drain pins C0.3 v dd + 0.3 1 v input voltage of true open drain pins C0.3 6 v i d instantaneous maximum current single pin limit (applies to all port pins) C25 25 ma v dda analog supply voltage v dd C 0.3 v dd + 0.3 v 1. maximum rating of v dd also applies to v in . ratings kea128 sub-family data sheet, rev4, 09/2014. 6 freescale semiconductor, inc.
general nonswitching electrical specifications 4.1.1 dc characteristics this section includes information about power supply requirements and i/o pin characteristics. table 2. dc characteristics symbol descriptions min typical 1 max unit operating voltage 2.7 5.5 v v oh output high voltage all i/o pins, except pta2 and pta3, standard-drive strength 5 v, i load = C5 ma v dd C 0.8 v 3 v, i load = C2.5 ma v dd C 0.8 v high current drive pins, high-drive strength 2 5 v, i load = C20 ma v dd C 0.8 v 3 v, i load = C10 ma v dd C 0.8 v i oht output high current max total i oh for all ports 5 v C100 ma 3 v C60 v ol output low voltage all i/o pins, standard-drive strength 5 v, i load = 5 ma 0.8 v 3 v, i load = 2.5 ma 0.8 v high current drive pins, high-drive strength 2 5 v, i load =20 ma 0.8 v 3 v, i load = 10 ma 0.8 v i olt output low current max total i ol for all ports 5 v 100 ma 3 v 60 v ih input high voltage all digital inputs 4.5v dd <5.5 v 0.65 v dd v 2.7v dd <4.5 v 0.70 v dd v il input low voltage all digital inputs 4.5v dd <5.5 v 0.35 v dd v 2.7v dd <4.5 v 0.30 v dd v hys input hysteresis all digital inputs 0.06 v dd mv |i in | input leakage current per pin (pins in high impedance input mode) v in = v dd or v ss 0.1 1 a table continues on the next page... 4 4.1 general kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 7
table 2. dc characteristics (continued) symbol descriptions min typical 1 max unit |i intot | total leakage combined for all port pins pins in high impedance input mode v in = v dd or v ss 2 a r pu pullup resistors all digital inputs, when enabled (all i/o pins other than pta2 and pta3) 30.0 50.0 k? r pu 3 pullup resistors pta2 and pta3 pins 30.0 60.0 k? i ic dc injection current 4 , 5 , 6 single pin limit v in < v ss , v in > v dd -2 2 ma total mcu limit, includes sum of all stressed pins -5 25 c in input capacitance, all pins 7 pf v ram ram retention voltage 2.0 v 1. typical values are measured at 25 c. characterized, not tested. 2. only ptb4, ptb5, ptd0, ptd1, pte0, pte1, pth0, and pth1 support high current output. 3. the specified resistor value is the actual value internal to the device. the pullup value may appear higher when measured externally on the pin. 4. all functional non-supply pins, except for pta2 and pta3, are internally clamped to v ss and v dd . pta2 and pta3 are true open drain i/o pins that are internally clamped to v ss . 5. input must be current limited to the value specified. to determine the value of the required current-limiting resistor, calculate resistance values for positive and negative clamp voltages, then use the larger value. 6. power supply must maintain regulation within operating v dd range during instantaneous and operating maximum current conditions. if the positive injection current (v in > v dd ) is higher than i dd , the injection current may flow out of v dd and could result in external power supply going out of regulation. ensure that external v dd load will shunt current higher than maximum injection current when the mcu is not consuming power, such as when no system clock is present, or clock rate is very low (which would reduce overall power consumption). table 3. lvd and por specification symbol description min typ max unit v por por re-arm voltage 1 1.5 1.75 2.0 v v lvdh falling low-voltage detect thresholdhigh range (lvdv = 1) 2 4.2 4.3 4.4 v v lvw1h falling low- voltage warning threshold high range level 1 falling (lvwv = 00) 4.3 4.4 4.5 v v lvw2h level 2 falling (lvwv = 01) 4.5 4.5 4.6 v v lvw3h level 3 falling (lvwv = 10) 4.6 4.6 4.7 v v lvw4h level 4 falling (lvwv = 11) 4.7 4.7 4.8 v v hysh high range low-voltage detect/ warning hysteresis 100 mv table continues on the next page... nonswitching electrical specifications kea128 sub-family data sheet, rev4, 09/2014. 8 freescale semiconductor, inc.
table 3. lvd and por specification (continued) symbol description min typ max unit v lvdl falling low-voltage detect thresholdlow range (lvdv = 0) 2.56 2.61 2.66 v v lvw1l falling low- voltage warning thresholdlow range level 1 falling (lvwv = 00) 2.62 2.7 2.78 v v lvw2l level 2 falling (lvwv = 01) 2.72 2.8 2.88 v v lvw3l level 3 falling (lvwv = 10) 2.82 2.9 2.98 v v lvw4l level 4 falling (lvwv = 11) 2.92 3.0 3.08 v v hysdl low range low-voltage detect hysteresis 40 mv v hyswl low range low-voltage warning hysteresis 80 mv v bg buffered bandgap output 3 1.14 1.16 1.18 v 1. maximum is highest voltage that por is guaranteed. 2. rising thresholds are falling threshold + hysteresis. 3. voltage factory trimmed at v dd = 5.0 v, temp = 125 c i oh (ma) v dd -v oh (v) figure 1. typical v dd -v oh vs. i oh (standard drive strength) (v dd = 5 v) nonswitching electrical specifications kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 9
i oh (ma) v dd -v oh (v) figure 2. typical v dd -v oh vs. i oh (standard drive strength) (v dd = 3 v) i oh ( ma ) v dd - v oh (v) figure 3. typical v dd -v oh vs. i oh (high drive strength) (v dd = 5 v) nonswitching electrical specifications kea128 sub-family data sheet, rev4, 09/2014. 10 freescale semiconductor, inc.
i oh (ma) v dd -v oh (v) figure 4. typical v dd -v oh vs. i oh (high drive strength) (v dd = 3 v) i ol ( ma ) v ol (v) figure 5. typical v ol vs. i ol (standard drive strength) (v dd = 5 v) nonswitching electrical specifications kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 11
i ol ( ma ) v ol (v) figure 6. typical v ol vs. i ol (standard drive strength) (v dd = 3 v) i ol ( ma ) v ol (v) figure 7. typical v ol vs. i ol (high drive strength) (v dd = 5 v) nonswitching electrical specifications kea128 sub-family data sheet, rev4, 09/2014. 12 freescale semiconductor, inc.
i ol ( ma ) v ol (v) figure 8. typical v ol vs. i ol (high drive strength) (v dd = 3 v) 4.1.2 supply current characteristics this section includes information about power supply current in various operating modes. table 4. supply current characteristics parameter symbol core/bus freq v dd (v) typical 1 max unit temp run supply current fei mode, all modules clocks enabled; run from flash ri dd 48/24 mhz 5 11.1 ma -40 to 125 c 24/24 mhz 8 12/12 mhz 5 1/1 mhz 2.4 48/24 mhz 3 11 24/24 mhz 7.9 12/12 mhz 4.9 1/1 mhz 2.3 run supply current fei mode, all modules clocks disabled and gated; run from flash ri dd 48/24 mhz 5 7.8 ma -40 to 125 c 24/24 mhz 5.5 12/12 mhz 3.8 1/1 mhz 2.3 table continues on the next page... nonswitching electrical specifications kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 13
table 4. supply current characteristics (continued) parameter symbol core/bus freq v dd (v) typical 1 max unit temp 48/24 mhz 3 7.7 24/24 mhz 5.4 12/12 mhz 3.7 1/1 mhz 2.2 run supply current fbe mode, all modules clocks enabled; run from ram ri dd 48/24 mhz 5 14.7 ma -40 to 125 c 24/24 mhz 9.8 14.9 2 12/12 mhz 6 1/1 mhz 2.4 48/24 mhz 3 14.6 24/24 mhz 9.6 12.8 2 12/12 mhz 5.9 1/1 mhz 2.3 run supply current fbe mode, all modules clocks disabled and gated; run from ram ri dd 48/24 mhz 5 11.4 ma -40 to 125 c 24/24 mhz 7.7 12.5 2 12/12 mhz 4.7 1/1 mhz 2.3 48/24 mhz 3 11.3 24/24 mhz 7.6 9.5 2 12/12 mhz 4.6 1/1 mhz 2.2 wait mode current fei mode, all modules clocks enabled wi dd 48/24 mhz 5 8.4 ma -40 to 125 c 24/24 mhz 6.5 7.2 2 12/12 mhz 4.3 1/1 mhz 2.4 48/24 mhz 3 8.3 24/24 mhz 6.4 7.1 2 12/12 mhz 4.2 1/1 mhz 2.3 stop mode supply current no clocks active (except 1 khz lpo clock) 3 si dd 5 2 170 2 a -40 to 125 c 3 1.9 160 2 -40 to 125 c adc adder to stop adlpc = 1 adlsmp = 1 adco = 1 mode = 10b adiclk = 11b 5 86 a -40 to 125 c 3 82 acmp adder to stop 5 12 a -40 to 125 c 3 12 table continues on the next page... nonswitching electrical specifications kea128 sub-family data sheet, rev4, 09/2014. 14 freescale semiconductor, inc.
table 4. supply current characteristics (continued) parameter symbol core/bus freq v dd (v) typical 1 max unit temp lvd adder to stop 4 5 130 a -40 to 125 c 3 125 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. the high current is observed at high temperature. 3. rtc adder cause <1 a i dd increase typically, rtc clock source is 1 khz lpo clock. 4. lvd is periodically woken up from stop by 5% duty cycle. the period is equal to or less than 2 ms. 4.1.3 emc performance electromagnetic compatibility (emc) performance is highly dependent on the environment in which the mcu resides. board design and layout, circuit topology choices, location and characteristics of external components as well as mcu software operation play a significant role in emc performance. the system designer must consult the following freescale applications notes, available on freescale.com for advice and guidance specifically targeted at optimizing emc performance. ? an2321: designing for board level electromagnetic compatibility ? an1050: designing for electromagnetic compatibility (emc) with hcmos microcontrollers ? an1263: designing for electromagnetic compatibility with single-chip microcontrollers ? an2764: improving the transient immunity performance of microcontroller-based applications ? an1259: system design and layout techniques for noise reduction in mcu- based systems switching specifications 4.2.1 control timing table 5. control timing num rating symbol min typical 1 max unit 1 system and core clock f sys dc 48 mhz 2 bus frequency (t cyc = 1/f bus ) f bus dc 24 mhz 3 internal low power oscillator frequency f lpo 0.67 1.0 1.25 khz 4 external reset pulse width 2 t extrst 1.5 t cyc ns table continues on the next page... 4.2 switching specifications kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 15
table 5. control timing (continued) num rating symbol min typical 1 max unit 5 reset low drive t rstdrv 34 t cyc ns 6 irq pulse width asynchronous path 2 t ilih 100 ns synchronous path 3 t ihil 1.5 t cyc ns 7 keyboard interrupt pulse width asynchronous path 2 t ilih 100 ns synchronous path t ihil 1.5 t cyc ns 8 port rise and fall time - normal drive strength (load = 50 pf) 4 t rise 10.2 ns t fall 9.5 ns port rise and fall time - high drive strength (load = 50 pf) 4 t rise 5.4 ns t fall 4.6 ns 1. typical values are based on characterization data at v dd = 5.0 v, 25 c unless otherwise stated. 2. this is the shortest pulse that is guaranteed to be recognized as a reset pin request. 3. this is the minimum pulse width that is guaranteed to pass through the pin synchronization circuitry. shorter pulses may or may not be recognized. in stop mode, the synchronizer is bypassed so shorter pulses can be recognized. 4. timing is shown with respect to 20% v dd and 80% v dd levels. temperature range -40 c to 125 c. ? ? ? ? ? ? ? ? t extrst reset_b pin figure 9. reset timing t ihil kbipx t ilih irq /kbipx figure 10. kbipx timing 4.2.2 ftm module timing synchronizer circuits determine the shortest input pulses that can be recognized or the fastest clock that can be used as the optional external source to the timer counter. these synchronizers operate from the current bus rate clock. table 6. ftm input timing function symbol min max unit timer clock frequency f timer f bus f sys hz external clock frequency f tclk 0 f timer /4 hz table continues on the next page... switching specifications kea128 sub-family data sheet, rev4, 09/2014. 16 freescale semiconductor, inc.
table 6. ftm input timing (continued) function symbol min max unit external clock period t tclk 4 t cyc external clock high time t clkh 1.5 t cyc external clock low time t clkl 1.5 t cyc input capture pulse width t icpw 1.5 t cyc ? ? ? ? ? ? ? ? t tclk t clkh t clkl tclk figure 11. timer external clock ? ? ? ? ? ? ? ? t icpw ftmchn t icpw ftmchn figure 12. timer input capture pulse thermal specifications 4.3.1 thermal characteristics this section provides information about operating temperature range, power dissipation, and package thermal resistance. power dissipation on i/o pins is usually small compared to the power dissipation in on-chip logic and voltage regulator circuits, and it is user- determined rather than being controlled by the mcu design. to take p i/o into account in power calculations, determine the difference between actual pin voltage and v ss or v dd and multiply by the pin current for each i/o pin. except in cases of unusually high pin current (heavy loads), the difference between pin voltage and v ss or v dd will be very small. 4.3 thermal specifications kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 17
table 7. thermal attributes board type symbol description 64 lqfp 80 lqfp unit notes single-layer (1s) r ja thermal resistance, junction to ambient (natural convection) 71 57 c/w 1 , 2 four-layer (2s2p) r ja thermal resistance, junction to ambient (natural convection) 53 44 c/w 1 , 3 single-layer (1s) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 59 47 c/w 1 , 3 four-layer (2s2p) r jma thermal resistance, junction to ambient (200 ft./min. air speed) 46 38 c/w 1 , 3 r jb thermal resistance, junction to board 35 28 c/w 4 r jc thermal resistance, junction to case 20 15 c/w 5 jt thermal characterization parameter, junction to package top outside center (natural convection) 5 3 c/w 6 1. junction temperature is a function of die size, on-chip power dissipation, package thermal resistance, mounting site (board) temperature, ambient temperature, air flow, power dissipation of other components on the board, and board thermal resistance. 2. per jedec jesd51-2 with the single layer board (jesd51-3) horizontal. 3. per jedec jesd51-6 with the board (jesd51-7) horizontal. 4. thermal resistance between the die and the printed circuit board per jedec jesd51-8. board temperature is measured on the top surface of the board near the package. 5. thermal resistance between the die and the solder pad on the bottom of the package. interface resistance is ignored. 6. thermal characterization parameter indicating the temperature difference between package top and the junction temperature per jedec jesd51-2. when greek letters are not available, the thermal characterization. the average chip-junction temperature (t j ) in c can be obtained from: t j = t a + (p d ja ) where: t a = ambient temperature, c ja = package thermal resistance, junction-to-ambient, c/w p d = p int + p i/o p int = i dd v dd , watts - chip internal power p i/o = power dissipation on input and output pins - user determined for most applications, p i/o << p int and can be neglected. an approximate relationship between p d and t j (if p i/o is neglected) is: p d = k (t j + 273 c) solving the equations above for k gives: k = p d (t a + 273 c) + ja (p d ) 2 thermal specifications kea128 sub-family data sheet, rev4, 09/2014. 18 freescale semiconductor, inc.
where k is a constant pertaining to the particular part. k can be determined by measuring p d (at equilibrium) for an known t a . using this value of k, the values of p d and t j can be obtained by solving the above equations iteratively for any value of t a . 5 peripheral operating requirements and behaviors 5.1 core modules 5.1.1 swd electricals table 8. swd full voltage range electricals symbol description min. max. unit operating voltage 2.7 5.5 v j1 swd_clk frequency of operation ? serial wire debug 0 24 mhz j2 swd_clk cycle period 1/j1 ns j3 swd_clk clock pulse width ? serial wire debug 20 ns j4 swd_clk rise and fall times 3 ns j9 swd_dio input data setup time to swd_clk rise 10 ns j10 swd_dio input data hold time after swd_clk rise 3 ns j11 swd_clk high to swd_dio data valid 35 ns j12 swd_clk high to swd_dio high-z 5 ns j2 j3 j3 j4 j4 swd_clk (input) figure 13. serial wire clock input timing peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 19
j11 j12 j11 j9 j10 input data valid output data valid output data valid swd_clk swd_dio swd_dio swd_dio swd_dio figure 14. serial wire data timing 5.2 external oscillator (osc) and ics characteristics table 9. osc and ics specifications (temperature range = -40 to 125 c ambient) num characteristic symbol min typical 1 max unit 1 crystal or resonator frequency low range (range = 0) f lo 31.25 32.768 39.0625 khz high range (range = 1) f hi 4 24 mhz 2 load capacitors c1, c2 see note 2 3 feedback resistor low frequency, low-power mode 3 r f m? low frequency, high-gain mode 10 m? high frequency, low-power mode 1 m? high frequency, high-gain mode 1 m? 4 series resistor - low frequency low-power mode 3 r s 0 k? high-gain mode 200 k? 5 series resistor - high frequency low-power mode 3 r s 0 k? series resistor - high frequency, high-gain mode 4 mhz 0 k? 8 mhz 0 k? table continues on the next page... peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. 20 freescale semiconductor, inc.
table 9. osc and ics specifications (temperature range = -40 to 125 c ambient) (continued) num characteristic symbol min typical 1 max unit 16 mhz 0 k? 6 crystal start-up time low range = 32.768 khz crystal; high range = 20 mhz crystal 4 , 5 low range, low power t cstl 1000 ms low range, high gain 800 ms high range, low power t csth 3 ms high range, high gain 1.5 ms 7 internal reference start-up time t irst 20 50 s 8 internal reference clock (irc) frequency trim range f int_t 31.25 39.0625 khz 9 internal reference clock frequency, factory trimmed , t = 125 c, v dd = 5 v f int_ft 37.5 khz 10 dco output frequency range fll reference = fint_t, flo, or fhi/rdiv f dco 40 50 mhz 11 factory trimmed internal oscillator accuracy t = 125 c, v dd = 5 v f int_ft -0.8 0.8 % 12 deviation of irc over temperature when trimmed at t = 25 c, v dd = 5 v over temperature range from -40 c to 125c f int_t -1 0.8 % 13 frequency accuracy of dco output using factory trim value over temperature range from -40 c to 125c f dco_ft -2.3 0.8 % 14 fll acquisition time 4 , 6 t acquire 2 ms 15 long term jitter of dco output clock (averaged over 2 ms interval) 7 c jitter 0.02 0.2 %f dco 1. data in typical column was characterized at 5.0 v, 25 c or is typical recommended value. 2. see crystal or resonator manufacturer's recommendation. 3. load capacitors (c 1 ,c 2 ), feedback resistor (r f ) and series resistor (r s ) are incorporated internally when range = hgo = 0. 4. this parameter is characterized and not tested on each device. 5. proper pc board layout procedures must be followed to achieve specifications. 6. this specification applies to any time the fll reference source or reference divider is changed, trim value changed, or changing from fll disabled (fbelp, fbilp) to fll enabled (fei, fee, fbe, fbi). if a crystal/resonator is being used as the reference, this specification assumes it is already running. 7. jitter is the average deviation from the programmed frequency measured over the specified interval at maximum f bus . measurements are made with the device powered by filtered supplies and clocked by a stable external clock signal. noise injected into the fll circuitry via v dd and v ss and variation in crystal oscillator frequency increase the c jitter percentage for a given interval. peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 21
osc extal crystal or resonator r s c 2 r f c 1 xtal figure 15. typical crystal or resonator circuit 5.3 nvm specifications this section provides details about program/erase times and program/erase endurance for the flash memories. table 10. flash characteristics characteristic symbol min 1 typical 2 max 3 unit 4 supply voltage for program/erase C40 c to 125 c v prog/erase 2.7 5.5 v supply voltage for read operation v read 2.7 5.5 v nvm bus frequency f nvmbus 1 24 mhz nvm operating frequency f nvmop 0.8 1 1.05 mhz erase verify all blocks t vfyall 2605 t cyc erase verify flash block t rd1blk 2579 t cyc erase verify flash section t rd1sec 485 t cyc read once t rdonce 464 t cyc program flash (2 word) t pgm2 0.12 0.13 0.31 ms program flash (4 word) t pgm4 0.21 0.21 0.49 ms program once t pgmonce 0.20 0.21 0.21 ms erase all blocks t ersall 95.42 100.18 100.30 ms erase flash block t ersblk 95.42 100.18 100.30 ms erase flash sector t erspg 19.10 20.05 20.09 ms unsecure flash t unsecu 95.42 100.19 100.31 ms verify backdoor access key t vfykey 482 t cyc set user margin level t mloadu 415 t cyc flash program/erase endurance t l to t h = -40 c to 125 c n flpe 10 k 100 k cycles table continues on the next page... peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. 22 freescale semiconductor, inc.
table 10. flash characteristics (continued) characteristic symbol min 1 typical 2 max 3 unit 4 data retention at an average junction temperature of t javg = 85c after up to 10,000 program/erase cycles t d_ret 15 100 years 1. minimum times are based on maximum f nvmop and maximum f nvmbus 2. typical times are based on typical f nvmop and maximum f nvmbus 3. maximum times are based on typical f nvmop and typical f nvmbus plus aging 4. t cyc = 1 / f nvmbus program and erase operations do not require any special power sources other than the normal v dd supply. for more detailed information about program/erase operations, see the flash memory module section in the reference manual. 5.4 analog 5.4.1 adc characteristics table 11. 5 v 12-bit adc operating conditions characteri stic conditions symbol min typ 1 max unit comment reference potential ? low ? high v refl v refh v ssa v dda /2 v dda /2 v dda v supply voltage absolute v dda 2.7 5.5 v delta to v dd (v dd -v dda ) v dda -100 0 +100 mv input voltage v adin v refl v refh v input capacitance c adin 4.5 5.5 pf input resistance r adin 3 5 k? analog source resistance 12-bit mode ? f adck > 4 mhz ? f adck < 4 mhz r as 2 5 k? external to mcu 10-bit mode ? f adck > 4 mhz ? f adck < 4 mhz 5 10 8-bit mode (all valid f adck ) 10 adc conversion clock frequency high speed (adlpc=0) f adck 0.4 8.0 mhz low power (adlpc=1) 0.4 4.0 peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 23
1. typical values assume v dda = 5.0 v, temp = 25c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. adc sar engine simplified channel select circuit simplified input pin equivalent circuit pad leakage due to input protection z as r as c as v adin v as z adin r adin r adin r adin r adin input pin input pin input pin c adin figure 16. adc input impedance equivalency diagram table 12. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) characteristic conditions symbol min typ 1 max unit supply current adlpc = 1 adlsmp = 1 adco = 1 i dda 133 a supply current adlpc = 1 adlsmp = 0 adco = 1 i dda 218 a supply current adlpc = 0 adlsmp = 1 adco = 1 i dda 327 a supply current adlpc = 0 adlsmp = 0 adco = 1 i dda 582 990 a supply current stop, reset, module off i dda 0.011 1 a table continues on the next page... peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. 24 freescale semiconductor, inc.
table 12. 12-bit adc characteristics (v refh = v dda , v refl = v ssa ) (continued) characteristic conditions symbol min typ 1 max unit adc asynchronous clock source high speed (adlpc = 0) f adack 2 3.3 5 mhz low power (adlpc = 1) 1.25 2 3.3 conversion time (including sample time) short sample (adlsmp = 0) t adc 20 adck cycles long sample (adlsmp = 1) 40 sample time short sample (adlsmp = 0) t ads 3.5 adck cycles long sample (adlsmp = 1) 23.5 total unadjusted error 2 12-bit mode e tue 5.0 lsb 3 10-bit mode 1.5 8-bit mode 0.8 differential non- liniarity 12-bit mode dnl 1.5 lsb 3 10-bit mode 0.4 8-bit mode 0.15 integral non-linearity 12-bit mode inl 1.5 lsb 3 10-bit mode 0.4 8-bit mode 0.15 zero-scale error 4 12-bit mode e zs 1.0 lsb 3 10-bit mode 0.2 8-bit mode 0.35 full-scale error 5 12-bit mode e fs 2.5 lsb 3 10-bit mode 0.3 8-bit mode 0.25 quantization error 12 bit modes e q 0.5 lsb 3 input leakage error 6 all modes e il i in x r as mv temp sensor slope -40 cC25 c m 3.266 mv/c 25 cC125 c 3.638 temp sensor voltage 25 c v temp25 1.396 v 1. typical values assume v dda = 5.0 v, temp = 25 c, f adck =1.0 mhz unless otherwise stated. typical values are for reference only and are not tested in production. 2. includes quantization 3. 1 lsb = (v refh - v refl )/2 n 4. v adin = v ssa 5. v adin = v dda 6. i in = leakage current (refer to dc characteristics) peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 25
5.4.2 analog comparator (acmp) electricals table 13. comparator electrical specifications characteristic symbol min typical max unit supply voltage v dda 2.7 5.5 v supply current (operation mode) i dda 10 20 a analog input voltage v ain v ss - 0.3 v dda v analog input offset voltage v aio 40 mv analog comparator hysteresis (hyst=0) v h 15 20 mv analog comparator hysteresis (hyst=1) v h 20 30 mv supply current (off mode) i ddaoff 60 na propagation delay t d 0.4 1 s 5.5 communication interfaces 5.5.1 spi switching specifications the serial peripheral interface (spi) provides a synchronous serial bus with master and slave operations. many of the transfer attributes are programmable. the following tables provide timing characteristics for classic spi timing modes. see the spi chapter of the chip's reference manual for information about the modified transfer formats used for communicating with slower peripheral devices. all timing is shown with respect to 20% v dd and 80% v dd , unless noted, and 25 pf load on all spi pins. all timing assumes slew rate control is disabled and high-drive strength is enabled for spi output pins. table 14. spi master mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation f bus /2048 f bus /2 hz f bus is the bus clock 2 t spsck spsck period 2 x t bus 2048 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1/2 t spsck 4 t lag enable lag time 1/2 t spsck 5 t wspsck clock (spsck) high or low time t bus C 30 1024 x t bus ns 6 t su data setup time (inputs) 8 ns 7 t hi data hold time (inputs) 8 ns 8 t v data valid (after spsck edge) 25 ns 9 t ho data hold time (outputs) 20 ns table continues on the next page... peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. 26 freescale semiconductor, inc.
table 14. spi master mode timing (continued) nu m. symbol description min. max. unit comment 10 t ri rise time input t bus C 25 ns t fi fall time input 11 t ro rise time output 25 ns t fo fall time output (output) 2 8 6 7 msb in 2 lsb in msb out 2 lsb out 9 5 5 3 (cpol=0) 4 11 11 10 10 spsck spsck (cpol=1) 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 1. if configured as an output. ss 1 (output) (output) mosi (output) miso (input) bit 6 . . . 1 bit 6 . . . 1 figure 17. spi master mode timing (cpha=0) <> <> 38 2 6 7 msb in 2 bit 6 . . . 1 master msb out 2 master lsb out 5 5 8 10 11 port data port data 3 10 11 4 1.if configured as output 2. lsbf = 0. for lsbf = 1, bit order is lsb, bit 1, ..., bit 6, msb. 9 (output) (cpol=0) spsck spsck (cpol=1) ss 1 (output) (output) mosi (output) miso (input) lsb in bit 6 . . . 1 figure 18. spi master mode timing (cpha=1) peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 27
table 15. spi slave mode timing nu m. symbol description min. max. unit comment 1 f op frequency of operation 0 f bus /4 hz f bus is the bus clock as defined in control timing . 2 t spsck spsck period 4 x t bus ns t bus = 1/f bus 3 t lead enable lead time 1 t bus 4 t lag enable lag time 1 t bus 5 t wspsck clock (spsck) high or low time t bus - 30 ns 6 t su data setup time (inputs) 15 ns 7 t hi data hold time (inputs) 25 ns 8 t a slave access time t bus ns time to data active from high-impedance state 9 t dis slave miso disable time t bus ns hold time to high- impedance state 10 t v data valid (after spsck edge) 25 ns 11 t ho data hold time (outputs) 0 ns 12 t ri rise time input t bus - 25 ns t fi fall time input 13 t ro rise time output 25 ns t fo fall time output 2 10 6 7 msb in bit 6 . . . 1 slave msb slave lsb out 11 5 5 3 8 4 13 note: not defined 12 12 11 see note 13 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) lsb in bit 6 . . . 1 figure 19. spi slave mode timing (cpha = 0) peripheral operating requirements and behaviors kea128 sub-family data sheet, rev4, 09/2014. 28 freescale semiconductor, inc.
2 6 7 msb in bit 6 . . . 1 msb out slave lsb out 5 5 10 12 13 3 12 13 4 slave 8 9 see note (input) (cpol=0) spsck spsck (cpol=1) ss (input) (input) mosi (input) miso (output) note: not defined 11 lsb in bit 6 . . . 1 figure 20. spi slave mode timing (cpha=1) 5.5.2 mscan table 16. mscan wake-up pulse characteristics parameter symbol min typ max unit mscan wakeup dominant pulse filtered t wup - - 1.5 s mscan wakeup dominant pulse pass t wup 5 - - s dimensions 6.1 obtaining package dimensions package dimensions are provided in package drawings. to find a package drawing, go to freescale.com and perform a keyword search for the drawings document number: if you want the drawing for this package then use this document number 64-pin lqfp 98ass23234w 80-pin lqfp 98ass23237w 6 dimensions kea128 sub-family data sheet, rev4, 09/2014. freescale semiconductor, inc. 29
pinout 7.1 signal multiplexing and pin assignments for the pin muxing details see section signal multiplexing and signal descriptions of kea128 reference manual. 8 revision history the following table provides a revision history for this document. table 17. revision history rev. no. date substantial changes rev. 1 11 march 2014 initial release rev. 2 18 june 2014 ? parameter classification section is removed. ? classification column is removed from all the tables in the document. ? new section added - supply current characteristics . rev. 3 18 july 2014 ? added supported part numbers. ? esd handling ratings section is updated. ? figures in dc characteristics section are updated. ? specs updated in following tables: ? table 9 . rev. 4 03 sept 2014 ? data sheet type changed to "technical data". 7 pinout kea128 sub-family data sheet, rev4, 09/2014. 30 freescale semiconductor, inc.
how to reach us: home page: freescale.com web support: freescale.com/support information in this document is provided solely to enable system and software implementers to use freescale products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits based on the information in this document. freescale reserves the right to make changes without further notice to any products herein. freescale makes no warranty, representation, or guarantee regarding the suitability of its products for any particular purpose, nor does freescale assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. typical parameters that may be provided in freescale data sheets and/or specifications can and do vary in different applications, and actual performance may vary over time. all operating parameters, including typicals, must be validated for each customer application by customer's technical experts. freescale does not convey any license under its patent rights nor the rights of others. freescale sells products pursuant to standard terms and conditions of sale, which can be found at the following address: freescale.com/salestermsandconditions . freescale, the freescale logo, and kinetis are trademarks of freescale semiconductor, inc., reg. u.s. pat. & tm. off. all other product or service names are the property of their respective owners. arm and cortex-m0+ are the registered trademarks of arm limited. ?2014 freescale semiconductor, inc. document number s9kea128p80m48sf0 revision 4, 09/2014

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